View LTC1755EGNPBF_9088738.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 ltc1755/ltc1756 smart card interface fully iso 7816-3 and emv compliant(including auxiliary i/o pins) buck-boost charge pump generates 3v or 5v 2.7v to 6.0v input voltage range (ltc1755) very low operating current: 60 m a > 10kv esd on all smart card pins dynamic pull-ups deliver fast signal rise times soft-start limits inrush current at turn on 3v ? 5v signal level translators shutdown current: < 1 m a short-circuit and overtemperature protected alarm output indicates fault condition multiple devices may be paralleled formulticard applications (ltc1755) available in 16- and 24-pin ssop packages the ltc 1755/ltc1756 universal smart card interfaces are fully compliant with iso 7816-3 and emv specifica-tions. the parts provide the smallest and simplest inter- face circuits between a host microcontroller and general purpose smart cards. an internal charge pump dc/dc converter delivers regu- lated 3v or 5v to the smart card, while on-chip level shifters allow connection to a low voltage controller. all smart card contacts are rated for 10kv esd, eliminating the need for external esd protection devices. input voltage may range from 2.7v to 6.0v, allowing direct connection to a battery. internal soft-start mitigates start- up problems that may result when the input power is provided by another regulator. multiple devices may be paralleled and connected to a single controller for multicard applications. battery life is maximized by 60 m a operating current and 1 m a shutdown current. the narrow ssop packages mini- mize pcb area for compact portable systems. , ltc and lt are registered trademarks of linear technology corporation. handheld payment terminals pay telephones atms key chain readers smart card readers features descriptio u applicatio s u typical applicatio u 12 3 4 5 6 7 8 9 1011 12 2423 22 21 20 19 18 17 16 15 14 13 ltc1755 prespwr cs nc/no gnd v in v cc aux1aux2 i/o rst clk c210 m f c3 10 m f v cc aux1aux2 i/o rst clk c10.68 m f gnd smart card 17556 ta01 smart card present switch m controller 3.3v 5v/3v card alarm ready dv cc c c + aux1inaux2in data rin cin downloaded from: http:///
2 ltc1755/ltc1756 order part number ltc1755egn t jmax = 125 c, q ja = 150 c/w consult factory for industrial and military grade parts. v in to gnd (ltc1755) ............................. 0.3v to 6.5v v in to gnd (ltc1756) ............................. 0.3v to 6.0v dv cc to gnd (ltc1755) .......................... 0.3v to 5.5v v cc to gnd .............................................. 0.3v to 5.5v digital inputs to gnd (ltc1755) .............................. 0.3v to dv cc + 0.3v digital inputs to gnd (ltc1756) ................................. 0.3v to v in + 0.3v (note 1) clk, rst, i/o, aux1, aux2 to gnd .............................. 0.3v to v cc + 0.3v v cc short-circuit duration ............................... indefinite operating temperature range (note 2) .. 40 c to 85 c storage temperature range ................ 65 c to 150 c lead temperature (soldering, 10 sec)................. 300 c absolute axi u rati gs w ww u package/order i for atio uu w 12 3 4 5 6 7 8 9 1011 12 top view gn package 24-lead narrow plastic ssop 2423 22 21 20 19 18 17 16 15 14 13 pres pwr cs nc/no gnd v in v cc aux1aux2 i/o rst clk 5v/3vcard alarm ready dv cc c c + aux1inaux2in data rin cin order part number ltc1756egn gn package 16-lead narrow plastic ssop 12 3 4 5 6 7 8 top view 1615 14 13 12 11 10 9 pres pwr gnd v in v cc i/o rst clk 5v/3vcard ready c c + datarin cin t jmax = 125 c, q ja = 135 c/w part marking 1756 downloaded from: http:///
3 ltc1755/ltc1756 the denotes specifications which apply over the full specified temperature range, otherwise specificatons are at t a = 25 c. electrical characteristics parameter conditions min typ max units ltc1755 (v in = 2.7v to 6v, dv cc = 2v to 5.5v, unless otherwise noted) v in operating voltage 2.7 6 v dv cc operating voltage 2.0 5.5 v i vin operating current active state, i vcc = 0 50 100 m a i dvcc operating current active state, dv cc = 3v 10 20 m a i vin shutdown current idle state, dv cc = 0v, v in 3.6v 1 m a idle state, dv cc = 0v, 3.6v < v in 6v 10 m a idle state, dv cc = 5.5v, v in 6v 20 m a v cc output voltage 5v/3v = dv cc 4.75 5.00 5.25 v 5v/3v = 0v 2.80 3.00 3.20 v i vcc output current 5v/3v = 0v 3v v in 6.0v 55 ma 5v/3v = dv cc 3v v in 6.0v 65 ma 5v/3v = 0v 2.7v v in 6.0v 55 ma 5v/3v = dv cc 2.7v v in 6.0v 40 ma v cc turn-on time c out = 10 m f, pwr to ready, 50% to 50% 2.7 12 ms v cc discharge time to 0.4v i vcc = 0ma, v cc = 5v, c out = 10 m f 100 250 m s ltc1756 (v in = 2.7v to 5.5v, unless otherwise noted) v in operating voltage 2.7 5.5 v i vin operating current active state, i vcc = 0 75 150 m a i vin shutdown current idle state, v in 3.6v 2.5 m a idle state, 3.6v < v in 5.5v 10 m a v cc output voltage 5v/3v = v in 4.75 5.00 5.25 v 5v/3v = 0v 2.80 3.00 3.20 v i vcc output current 5v/3v = 0v 3v v in 5.5v 55 ma 5v/3v = v in 3v v in 5.5v 65 ma 5v/3v = 0v 2.7v v in 5.5v 55 ma 5v/3v = v in 2.7v v in 5.5v 40 ma v cc turn-on time c out = 10 m f, pwr to ready, 50% to 50% 2.7 12 ms v cc discharge time to 0.4v i vcc = 0ma, v cc = 5v, c out = 10 m f 100 250 m s downloaded from: http:///
4 ltc1755/ltc1756 the denotes specifications which apply over the full specified temperature range, otherwise specificatons are at t a = 25 c. dv cc = 2v to 5.5v, unless otherwise noted (note 4). note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired.note 2: the ltc1755/ltc1756 are guaranteed to meet performance specifications from 0 c to 70 c. specifications over the 40 c to 85 c operating temperature range are assured by design, characterization andcorrelation with statistical process controls. note 3: the data, aux1in, aux2in, aux1, aux2 and i/o pull-down drivers must sink up to 250 m a sourced by the internal current sources. note 4: on the ltc1756, dv cc is internally connected to the v in pin. specifications that call out dv cc should be referred to v in instead. parameter conditions min typ max units controller inputs/outputs data, aux1in, aux2in, dv cc = 3v high input voltage threshold (v ih ) (note 4) dv cc ?0.6 0.5 ?dv cc v low input voltage threshold (v il ) (note 4) 0.5 ?dv cc 0.3 v high level output voltage (v oh ) source current = 20 m a (note 4) 0.7 ?dv cc v low level output voltage (v ol ) sink current = 500 m a (note 3) 0.3 v output rise/fall time loaded with 30pf, 10% to 90% 0.5 m s input current (i ih /i il ) cs = dv cc ? 1 m a rin, cin, pwr, cs, 5v/3v, nc/no high input voltage threshold (v ih ) (note 4) 0.7 ?dv cc 0.5 ?dv cc v low input voltage threshold (v il ) (note 4) 0.5 ?dv cc 0.2 ?dv cc v input current (i ih /i il ) ? 1 m a ready, alarm, card pull-up current (i oh ) 250 na low level output voltage (v ol ) sink current = 20 m a 0.3 v smart card inputs/outputs i/o, aux1, aux2, v cc = 3v or 5v high input voltage threshold (v ih )i ih(max) = 20 m a 0.6 ?v cc 0.5 ?v cc v low input voltage threshold (v il )i il(max) = 1ma 0.5 ?v cc 0.8 v high level output voltage (v oh ) source current = 20 m a 0.8 ?v cc v data, aux1in, aux2in = dv cc low level output voltage (v ol ) sink current = 1ma 0.3 v data, aux1in, aux2in = 0v (note 3) rise/ fall time loaded with 30pf, 10% to 90% 0.5 m s short-circuit current shorted to v cc 3.5 7.5 ma clk high level output voltage (v oh ) source current = 100 m a v cc ?0.5 v low level output voltage (v ol ) sink current = 200 m a 0.3 v clk rise/fall time clk loaded with 30pf 16 ns clk frequency clk loaded with 30pf 5 mhz rst high level output voltage (v oh ) source current = 200 m a 0.8 ?v cc v source current = 50 m a v cc ?0.5v v low level output voltage (v ol ) sink current = 200 m a 0.3 v rst rise/fall time loaded with 30pf, 10% to 90% 0.5 m s pres high input voltage threshold (v ih ) (note 4) 0.7 ?dv cc 0.5 ?dv cc v low input voltage threshold (v il ) (note 4) 0.5 ?dv cc 0.2 ?dv cc v pres pull-up current v pres = 0v 0.5 1 m a pres debounce time proportional to the 0.68 m f charge pump capacitor 40 80 ms electrical characteristics downloaded from: http:///
5 ltc1755/ltc1756 typical perfor a ce characteristics uw power efficiency vs input voltage card detection debounce periodvs temperature v in input voltage (v) 3 0 efficiency (%) 25 50 75 100 45 17556 g01 6 i l = 35ma t a = 25 c v cc = 3v v cc = 5v temperature ( c) ?0 0 debounce delay (ms) 25 50 75 100 150 ?5 02 55 0 17556 g02 75 100 125 c fly = 0.68 f v in = 6v v in = 3.3v v in = 2.7v temperature ( c) ?0 3.3 i/o, aux1, aux2 short-circiut current (ma) 3.4 3.5 3.6 ?5 02 55 0 17556 g03 75 100 v cc = 5v v in = 3v i/o, aux1, aux2 short-circuitcurrent vs temperature card, ready, alarm pull-upcurrent vs temperature temperature ( c) ?0 0 pull-up current ( a) 2 4 6 8 10 ?5 02 55 0 17556 g04 75 100 dv cc = 5.5v dv cc = 3v dv cc = 2v dv cc input voltage (v) 2 pull-up current ( a) 8 10 12 17556 g05 6 4 3 45 2 0 v pres = 0v t a = 25 c dv cc input voltage (v) 1 5 input current ( a) 10 15 20 25 35 2 345 17556 g02 67 30 v pres = 0v t a = 40 ct a = 25 c t a = 85 c pres pin pull-up current vs dv cc dv cc input current vs dv cc voltage oscillator frequencyvs temperature temperature ( c) ?0 500 oscillator frequency (khz) 600 700 800 900 1100 ?5 02 55 0 17556 g07 75 100 1000 v in = 5v v in = 3.3v v in = 2.7v oscillator frequencyvs input voltage v in input voltage (v) 2.5 500 oscillator frequency (khz) 600 700 800 900 1100 3.0 3.5 4.0 4.5 17556 g07 5.0 5.5 1000 t a = 85 c t a = 25 c t a = 40 c v in supply current vs temperature temperature ( c) ?0 40 supply current ( a) 50 60 70 ?5 02 55 0 17556 g09 75 100 v in = 3.3v i cc = 0 downloaded from: http:///
6 ltc1755/ltc1756 typical perfor a ce characteristics uw dv cc , v in supply current in shutdown dv cc input voltage (v) 0 0 input current ( a) 3.0 6.0 9.0 1.5 4.5 7.5 dv cc v in 1 234 17556 g10 56 v in = 3v t a = 25 c v in shutdown current vs input voltage input voltage (v) 0 0 input current ( a) 0.2 0.4 0.6 0.8 1.0 1 234 17556 g11 56 dv cc = 0 t a = 25 c uu u pi fu ctio s pres (pin 1): (input) connects to the smart card acceptor? present indicator switch to detect if a card is inserted.this pin has a pull-up current source so that a grounded switch can be detected with no external components. the pull-up current source is nonlinear, delivering higher current when the pres pin is above 1v but very little current below 1v. this helps resist false card indications due to leakage current. the activation state of the pres pin can be set by the nc/no pin so that both normally open (no) and normally closed (nc) switches are easily recog- nized (see nc/no pin description). dv cc sets the logic reference level for the pres pin. pwr (pin 2): (input) a low on the pwr pin places the ltc1755/ltc1756 in the active state enabling the chargepump. the ready pin indicates when the card supply voltage (v cc ) has reached its final value and communica- tion with the smart card is possible. the reset and clockchannels are enabled after ready goes low. the three i/ o channels are also enabled only after ready goes low, however they may be disabled separately via the cs pin (cs is not available on the ltc1756). the falling edge of pwr latches the state of the 5v/3v pin. after pwr is low, changes on the 5v/3v pin are ignored. cs (pin 3, ltc1755 only): (input) the cs pin enables the three bidirectional i/o channels of the ltc1755. when thei/o channels are disabled the smart card pins (i/o, aux1, aux2) are forced to logic one and the controller pins (data, aux2in, aux1in) are high impedance. cs can be brought low along with pwr when the device is first enabled, however communication with the smart card is inhibited until v cc reaches its final value as indicated by a low on the ready pin. cs does not affect the chargepump, clk or rst channels. on the ltc1756, cs is internally connected to the pwr pin. dv cc sets the logic reference level for the cs pin. nc/no (pin 4, ltc1755 only): (input) this pin controls the activation level of the pres pin. when it is high (dv cc ) the pres pin is active high. when it is low (gnd) the prespin is active low. in either case the presence of a smart card is indicated by a low on the card output. when a ground side normally open (no) switch is used the nc/no pin should be grounded. when a ground side normally closed (nc) switch is used the nc/no pin should be connected to dv cc . the ltc1756 is permanently config- ured to accept a normally open switch. ltc1755/ltc1756 downloaded from: http:///
7 ltc1755/ltc1756 note: if a normally closed switch is used, a small current (several microamperes) will flow through the switch when-ever a smart card is not present. for ultralow power consumption in shutdown, a normally open switch is optimum. dv cc sets the logic reference level for the nc/no pin. gnd (pins 5/3): ground reference for the ic. this pin should be connected to a low impedance ground plane.bypass capacitors for v in and v cc should be in close proximity to the gnd pin.v in (pins 6/4): supply voltage for the charge pump. may be between 2.7v and 6v. a 10 m f low esr ceramic bypass capacitor is required on this pin for optimum performance.v cc (pins 7/5): regulated smart card supply voltage. this pin should be connected to the smart card v cc contact. the 5v/3v pin determines the v cc output voltage. the v cc pin is protected against short circuits by compar- ing the actual output voltage with an internal referencevoltage. if v cc is below its correct level (for as little as 5 m s) the ltc1755/ltc1756 switch to the alarm state (see thestate diagram). the v cc pin requires a 10 m f charge storage capacitor to ground. for optimum performance alow esr ceramic capacitor should be used. during the idle and alarm states the v cc pin is rapidly discharged to ground to comply with the deactivationrequirements of the emv and iso-7816 specifications. aux1 (pin 8, ltc1755 only): (input/output) smart card side auxiliary i/o pin. this pin is used for auxiliarybidirectional data transfer between the microcontroller and the smart card. it has the same characteristics as the i/o pin. aux2 (pin 9, ltc1755 only): (input/output) smart card side auxiliary i/o pin. this pin is used for auxiliarybidirectional data transfer between the microcontroller and the smart card. it has the same characteristics as the i/o pin. i/o (pins 10/6): (input/output) smart card side data i/o pin. this pin is used for bidirectional data transfer betweenthe microcontroller and the smart card. it should be con- nected to the smart card i/o contact. the smart card i/o pin must be able to sink up to 250 m a when driving the i/o pin low due to the pull-up current source. the i/o pin be-comes a low impedance to ground during the idle state. it does not become active until ready goes low indicating that v cc is stable. once ready is low the i/o pin is protected against shortcircuits to v cc by current limiting to 5ma maximum. the data-i/o channel is bidirectional for half-duplextransmissions. its idle state is h-h. once an l is detected on one side of the channel the direction of transmission is established. specifically, the side which received an l first is now the input, and the opposite side is the output. transmission from the output side back to the input side is inhibited, thereby preventing a latch condition. once the input side releases its l, both sides return to h, and the channel is now ready for a new l to be transmitted in either direction. if an l is forced externally on the output side, and it persists until after the l on the input side is released, this illegal input will not be transmitted to the input side because the transmission direction will not have changed. the direction of transmission can only be established from the idle (h-h) state and is determined by the first receipt of an l on either side. rst (pins 11/7): (output) level-shifted reset output pin. this pin should be connected to the smart card rstcontact. the rst pin becomes a low impedance to ground during the idle state (see the state diagram). the reset channel does not become active until the ready signal goes low indicating that v cc is stable. short-circuit protection is provided on the rst pin bycomparing rst with r in . if these signals differ for several microseconds then the ltc1755/ltc1756 switch to thealarm state. this fault checking is only performed after the v cc pin has reached its final value (as indicated by the ready pin).clk (pins 12/8): (output) level-shifted clock output pin. this pin should be connected to the smart card clkcontact. the clk pin becomes a low impedance to ground during the idle state (see the state diagram). the clock channel does not become active until the ready signal goes low indicating that v cc is stable. short-circuit protection is provided on the clk pin bycomparing clk with c in . if these signals differ for several uu u pi fu ctio s ltc1755/ltc1756 downloaded from: http:///
8 ltc1755/ltc1756 microseconds then the ltc1755/ltc1756 switch to thealarm state. this fault checking is only performed after the v cc pin has reached its final value (as indicated by the ready pin).the clock channel is optimized for signal integrity in order to meet the stringent duty cycle requirements of the emv specification. therefore, to reduce power in low power applications, clock stop mode is recommended when data is not being exchanged. cin (pins 13/9): (input) clock input pin from the micro- controller. during the active state this signal appears onthe clk pin after being level-shifted and buffered. dv cc sets the logic reference level for the c in pin. rin (pins 14/10): (input) reset input pin from the micro- controller. during the active state this signal appears onthe rst pin after being level-shifted and buffered. dv cc sets the logic reference level for the r in pin. data (pins 15/11): (input/output) microcontroller side data i/o pin. this pin is used for bidirectional data transferbetween the microcontroller and the smart card. the microcontroller data pin must be open drain and must be able to sink up to 250 m a when driving the data pin low due to the pull-up current source. the data pin becomeshigh impedance during the idle state or when cs is high (see the state diagram). it does not become active until the ready signal goes low indicating that v cc is stable. aux2in (pin 16, ltc1755 only): (input/output) micro- controller side auxiliary i/o pin. this pin is used forbidirectional auxiliary data transfer between the micro- controller and the smart card. it has the same character- istics as the data pin. aux1in (pin 17, ltc1755 only): (input/output) micro- controller side auxiliary i/o pin. this pin is used forbidirectional auxiliary data transfer between the micro- controller and the smart card. it has the same character- istics as the data pin. c + , c (pins 18/12, 19/13): charge pump flying capaci- tor terminals. optimum values for the flying capacitorrange from 0.68 m f to 1 m f. best performance is achieved with a low esr x7r ceramic capacitor. dv cc (pin 20, ltc1755 only): supply voltage for the microcontroller side digital input and input/output pins(typically 3v). if the charge pump input pin (v in ) is powered from the same source as the microcontroller,then dv cc should be connected directly to v in . in this case only one (10 m f) input bypass capacitor is needed for the ltc1755. if the dv cc pin is powered separately then it should be bypassed separately with a 0.1 m f capacitor. the dv cc pin may be between 2v and 5.5v. the dv cc pin is monitored for adequate voltage. if dv cc drops below approximately 1.5v the ltc1755 automati-cally enters the idle state. on the ltc1756, dv cc is connected internally to v in . ready (pins 21/14): (output) readiness indicator of the smart card supply voltage (v cc ). when the ltc1755/ ltc1756 are placed in the active state the soft-startfeature slowly ramps the v cc voltage. a low on the ready pin indicates that v cc has reached its final value. the ready pin also indicates if the ltc1756 is in alarmmode. the ltc1756 detects faults such as v cc underrange for at least 5 m s, overtemperature shutdown, clk or rst invalid output levels and card removal during activestate. clk or rst invalid and overtemperature faults are detected only after v cc has reached its final value. v cc underrange and card removal during active faults aredetected at any time during the active period (i.e., once pwr = 0v). if the ltc1756 has been activated normally and v cc , the card voltage, has reached its final value then ready willgo low indicating normal operation. if, following this, a fault occurs and the ltc1756 enters the alarm state, the ready pin will return high. in the event that a fault precedes the activation of v cc , such as a direct short circuit from v cc to gnd, the ltc1756 will attempt to operate until the fault is detectedand then automatically shut down and enter the alarm state. in this case the ready pin will never go low after the command to start the smart card is given (i.e., pwr = 0v). if the ltc1755/ltc1756 enter the alarm state they canonly be cleared by returning the pwr pin high. uu u pi fu ctio s ltc1755/ltc1756 downloaded from: http:///
9 ltc1755/ltc1756 the ready pin is configured as an open-drain pull-downwith a weak pull-up current source. this permits wired- or connections of multiple ltc1755/ltc1756s to a single microcontroller. alarm (pin 22, ltc1755 only): (output) a low on this pin indicates that a fault has occurred and that the ltc1755is in the alarm state (see the state diagram). possible faults include v cc underrange for at least 5 m s, overtem- perature shutdown, clk or rst invalid output levels, andcard removal during the active state. clk or rst invalid and overtemperature faults are de- tected only after v cc has reached its final value (as indicated by the ready pin). v cc underrange and card removal during active faults are detected at any timeduring the active period (i.e., once pwr = 0v). the alarm pin is configured as an open-drain pull-downwith a weak pull-up current source. this permits wired- or connections of multiple ltc1755s to a single micro- controller. uu u pi fu ctio s ltc1755/ltc1756 card (pin 23/15): (output) level-shifted and debounced pres signal from the smart card acceptor switch. whena valid card indication appears, this pin communicates the presence of the smart card to the microcontroller. the card pin has an open-drain active pull-down with a weak pull-up current source for logic-or connections. the debounce circuit ensures that a card has been present for a continuous period of at least 40ms before asserting card low. the card pin returns high within 50 m s of card removal. the pres pin, in conjunction with the nc/no pin,determines if a card is present. 5v/3v (pin 24/16): (input) controls the output voltage (v cc ) of the dc/dc converter during the active state. a valid high sets v cc to 5v. a valid low sets v cc to 3v. the 5v/3v pin is latched on the falling edge of the pwr pin.when pwr is low, changes on the 5v/3v pin are ignored. to change the voltage on v cc the ltc1755/ltc1756 must first be returned to the idle state by bringing the pwr pinhigh. dv cc sets the logic reference level for the 5v/3v pin. downloaded from: http:///
10 ltc1755/ltc1756 block diagra w * * * * * * dv cc pres pwr t dc/dc converter and control logic cs (ltc1755 only) nc/no (ltc1755 only) gnd v in v cc aux1 (ltc1755 only) aux2 (ltc1755 only) i/o rst clk 17556 bd * dynamic pull-up current source 5v/3vcard alarm (ltc1755 only) ready dv cc (ltc1755 only,connected internally to v in on ltc1756) c c + aux1in(ltc1755 only) aux2in (ltc1755 only) data r in c in downloaded from: http:///
11 ltc1755/ltc1756 10kv esd protectionall smart card pins (clk, rst, i/o, aux1, aux2, v cc and gnd) can withstand over 10kv of human body model esdin situ. in order to ensure proper esd protection, careful board layout is required. the gnd pin should be tied directly to a ground plane. the v cc capacitor should be located very close to the v cc pin and tied immediately to the ground plane.capacitor selection the style and value of capacitors used with the ltc1755/ ltc1756 determine several parameters such as output ripple voltage, charge pump strength, smart card switch debounce time and v cc discharge rate. due to the switching nature of a capacitive charge pump,low equivalent series resistance (esr) capacitors are recommended for the capacitors at v in and v cc . when- ever the flying capacitor is switched to the v cc charge storage capacitor, considerable current flows. the prod-uct of this high current and the esr of the output capacitor can generate substantial voltage spikes on the v cc output. these spikes may cause problems with the smart card ormay interfere with the regulation loop of the ltc1755/ ltc1756. therefore, ceramic or tantalum capacitors are recommended rather than higher esr aluminum capaci- tors. between ceramic and tantalum, ceramic capacitors generally have the lowest esr. some manufacturers have developed low esr tantalum capacitors but they can be expensive and may still have higher esr than ceramic types. thus, while they cannot be avoided, esr spikes will typically be lowest when using ceramic capacitors. for ceramic capacitors there are several different materi- als available to choose from. the choice of ceramic material is generally based on factors such as available capacitance, case size, voltage rating, electrical perfor- mance and cost. for example, capacitors made of y5v material have high packing density, which provides high capacitance for a given case size. however, y5v capaci- tors tend to lose considerable capacitance over the 40 c to 85 c temperature range. x7r ceramic capacitors are more stable over temperature but don? provide the highpacking density. therefore, large capacitance values are generally not available in x7r ceramic. the value and style of the flying capacitor are importantnot only for the charge pump but also because they provide the large debounce time for the smart card detection channel. a 0.68 m f x7r capacitor is a good choice for the flying capacitor because it provides fairlyconstant capacitance over temperature and its value is not prohibitively large. the charge storage capacitor on the v cc pin determines the ripple voltage magnitude and the discharge time of thesmart card voltage. to minimize ripple, generally, a large value is needed. however, to meet the v cc discharge rate specification, the value should not exceed 20 m f. a 10 m f capacitor can be used but the ripple magnitude will behigher leading to worse apparent dc load regulation. typically a 15 m f to 18 m f y5v ceramic capacitor is the best choice for the v cc charge storage capacitor. for best performance, this capacitor should be connected as closeas possible to the v cc and gnd pins. note that most of the electrostatic discharge (esd) current on the smart cardpins is absorbed by this capacitor. the bypass capacitor at v in is also important. large dips on the input supply due to esr may cause problems withthe internal circuitry of the ltc1755/ltc1756. a good choice for the input bypass capacitor is a 10 m f y5v style ceramicdynamic pull-up current sources the current sources on the bidirectional pins (data, aux2in, aux1in, i/o, aux2 and aux1) are dynamically activated to achieve a fast rise time with a relatively small static current (figure 1). once a bidirectional pin is relin- quished, a small start-up current begins to charge the node. an edge rate detector determines if the pin is figure 1. dynamic pull-up current sources + d v d t i start 17556 f01 v ref bidirectional pin v cc or dv cc applicatio s i for atio wu uu downloaded from: http:///
12 ltc1755/ltc1756 5v/ m s, the following expression for r pull-up should be applied: r vv cp f pull up supply par - = () () C C 1 50 5 10 6 where c par is the extra capacitance on the bidirectional pin and v supply is the minimum local supply for the bidirectional pin. for example, on the smart card side, 3vshould be assumed for v supply . note that the addition of a pull-up resistor will give a higheroutput voltage when the bidirectional pin pulls down. care should be taken so that the v il or v ol specifications are not compromised with this technique.bidirectional channels as described in pin functions (pins 10/6), the bidirec- tional channels allow transmission in only one direction at a time. figure 2 shows a simplified block diagram of one of the three bidirectional channels. the three channels operate in an identical fashion. figure 3 shows an example of normal transmit and receive operations as well as the two possible collision scenarios. if a channel is activated from one direction and an l is imposed in the other direction before both sides return h a collision results. the result of the collision is that the receiving side ( slave side ) will remain low until it is released, but the transmitting side (first side to go low or master side ), will be allowed to return high if released. the colliding l externally imposed on the slave side will not betransmitted back through the channel. released by comparing its slew rate with an internalreference value. if a valid transition is detected, a large pull-up current enhances the edge rate on the node. the higher slew rate corroborates the decision to charge the node thereby effecting a dynamic form of hysteresis. once the node has reached the power supply voltage the internal comparator requires several hundred nanoseconds to reset. pulling down on the pin before the reset delay expires will result in a momentary contention and a higher current flow. therefore, the comparator delay sets the upper limit on the maximum data rate of the bidirectional channels to about 500khz. the dynamic pull-up current sources are designed to trigger with as much as 50pf of capacitive load on the bidirectional pins. at approximately 90pf (or greater), the edge rate on the node will be insufficient to trigger the edge rate detector and the node will only ramp up at a rate given by the i start current source and the load capacitance. in these instances the edge rate of the bidirectional pin maynot meet the requirements of existing smart card stan- dards. therefore, it is recommended that the sum of both explicit and parasitic capacitances on the bidirectional pins be kept below 50pf. if excessive capacitance (either explicit or parasitic) ispresent on the bidirectional pins, the starting pull-up current must also be increased. this can be accomplished with a pull-up resistor to the respective supply. for the smart card side (i/o, aux1 and aux2), the pull-up resis- tor should be connected to v cc . for the microcontroller side (data, aux1in and aux2in), the pull-up resistorshould be connected to dv cc on the ltc1755 (v in on the ltc1756). to maintain an edge rate of approximately applicatio s i for atio wu uu dv cc cs data charge pump bidirectional latch i/o to smart card to microcontroller v cc ready 3.5ma 17756 f02 figure 2. bidirectional channel simplified block diagram downloaded from: http:///
13 ltc1755/ltc1756 less than 10 m a. if dv cc is 0v the current drops below 1 m a. when a smart card is present the ltc1755/ltc1756operate with a quiescent current of only 60 m a, thus the majority of power is consumed by charge pump lossesand the card itself. if the card can be made to consume less power during idle times a significant power savings will be achieved. whenever possible clock stop mode should be used (or alternatively a very low ?dling?clock speed). furthermore, in the active state, the bidirectional pins should all be relinquished whenever possible since there is some static current flow when a bidirectional pin is pulled down. ltc1755 * 2n7002t1 (motorola) tn2460t (temic/siliconix) i/o r1 20k tosmart card 17556 f04 *connect gate to v cc for dv cc = 5v applications connect gate to dv cc or dv cc logic level signal for dv cc 3.3v applicatons 5v power to microcontroller data mn1 v cc dv cc figure 4. i 2 c level translation technique i 2 c tm compatibility some smart cards still require i 2 c compatibility. in the i 2 c format it is permissible to impose an l before the signalline has returned h. this is used, for example, as an acknowledge signal. such a scenario will cause a collision as shown in figure 3. figure 4 shows an analog level translation technique that can be used along with the ltc1755 to support i 2 c smart cards. in this technique it is important to connect the gateof the external mosfet to the lower of the two supplies (i.e., the lower of v cc or dv cc ). if dv cc is operating from a fixed 5v supply, the gate of mn1 should be connected tov cc . if dv cc is operating from a regulated 3.3v supply, the gate of mn1 should be connected to dv cc . in the latter case, the gate may need to be connected to a digital signalranging from 0v to dv cc so that it can be disabled when the ltc1755 is in shutdown. otherwise, the the ltc1755will try to assert an l on the microcontroller side of the channel when it is in shutdown. supporting synchronous and asyncronous cards in synchronous/asynchronous applications it is neces- sary to switch the clk pin of the card socket from a free running asynchronous clock to a controlled syncronous clock. to avoid glitches and pulses shorter than the minimum allowed pulse width, the circuit shown in figure 5 should be used as a clock selection circuit. note that for this circuit to be effective the sync input should be held constant while switching the async\sync control signal. low power operation the ltc1755/ltc1756 are inherently low power devices. when there is no smart card present the supply current is q q d to c in 17556 f05 q async sync async in sync in q d figure 5. glitchless clock selection circuit applicatio s i for atio wu uu i 2 c is a trademark of philips electronics n.v. data i/o normal transmit normal receive i/o pulled low during transmit mode (collision) data pulled low during receive mode (collision) 17556 f03 figure 3. possible bidirectional channel scenarios downloaded from: http:///
14 ltc1755/ltc1756 applicatio s i for atio wu uu figure 7. deactivation sequence v cc 1755 f07 rst clk i/o aux2aux1 rst = r in deactivation directive clk = c in i/o = data gnd v in v cc 17556 f08 figure 8. optimum bypass capacitor placement overtemperature fault protectionan overtemperature circuit disables the chip and activates the alarm pin if the ic? junction temperature exceeds 150 c. self-start modeby connecting the card pin to the pwr pin, the ltc1755/ ltc1756 can be made to start up automatically when a smart card is detected (figure 6). in this mode, the ready pin becomes an interrupt signal indicating to the micro- controller that a smart card is present and that v cc , the charge pump voltage, is at its final value. the smart cardremains powered as long as it is detected by the pres pin. when the smart card is removed the ltc1755/ltc1756 will automatically be deactivated by the fault detection circuitry. deactivation sequence for maximum flexibility the smart card can be deactivated either manually or automatically. in manual mode the de- activation is controlled by explicitly manipulating the ltc1755/ltc1756 input and control pins (data, aux1in, aux2in, rin and cin followed by pwr and cs). in auto- matic mode the pwr pin is used to perform the built-in figure 6. self-start mode card tomicrocontroller pwr ready 1755 f06 deactivation sequence. once pwr is brought high the built-in deactivation sequence occurs as shown in figure 7. in the event of a fault, the ltc1755/ltc1756 automatically implement the built-in deactivation sequence. pc board layout for best performance, the v in and v cc capacitors should be placed as close to the ltc1755/ltc1756 as possible.this will help reduce ringing due to inductance on the v in and v cc pins that could cause problems with the ltc1755/ ltc1756 control circuitry or smart card. figure 8 illus-trates a possible layout technique using only a single layer of the pc board. state definitions idle/deactivation v cc , rst, clk, i/o aux2, aux1 = l ready, alarm, data, aux2in, aux1in = zcard = pres ? nc/no once the ltc1755/ltc1756 enter the idle/deactivationstate the deactivation sequence begins. the deactivation sequence will continue until v cc is discharged to approxi- mately 1v. an activation command (pwr = 0v) will only beacknowledged once this occurs. alarm/deactivation same as idle/deactivation except: alarm = l downloaded from: http:///
15 ltc1755/ltc1756 applicatio s i for atio wu uu figure 9. ltc1755/ltc1756 state diagram deactivation no fault fault 1755 f09 power off idle deactivation alarm active fault timeout pwr = dv cc pwr = dv cc pwr = 0v pres nc/no fault > 5 m s or pres nc/no the only possible next state is idle/deactivation which isachieved by disabling the ltc1755/ltc1756 via the pwr pin (i.e., pwr = dv cc ). the alarm indication can be cleared by rapidly cycling thepwr pin. however, a new activation cycle will not begin until v cc is or has dropped below approximately 1v. activev cc = 3v or 5v (as determined by the 5v/3v pin) rst = r in , clk = c in i/o, aux2, aux1, data, aux2in, aux1in = ready fordata (after ready becomes low) card = pres ? nc/no alarm = h fault timeoutsame as active except: the duration of a fault is being measured. if the fault duration exceeds 5 m s then the alarm/deactivation state follows. if the fault duration is less than 5 m s, then the device is returned to the active state. dimensions in inches (millimeters) unless otherwise noted. gn package 16-lead plastic ssop (narrow 0.150) (ltc dwg # 05-08-1641) u package descriptio gn package 24-lead plastic ssop (narrow 0.150) (ltc dwg # 05-08-1641) gn16 (ssop) 1098 * dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side ** dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side 0.016 ?0.050 (0.406 ?1.270) 0.015 0.004 (0.38 0.10) 45 0 ?8 typ 0.007 ?0.0098 (0.178 ?0.249) 0.053 ?0.068 (1.351 ?1.727) 0.008 ?0.012 (0.203 ?0.305) 0.004 ?0.0098 (0.102 ?0.249) 0.0250 (0.635) bsc 12 3 4 5 6 7 8 0.229 ?0.244 (5.817 ?6.198) 0.150 ?0.157** (3.810 ?3.988) 16 15 14 13 0.189 ?0.196* (4.801 ?4.978) 12 11 10 9 0.009 (0.229) ref gn24 (ssop) 1098 * dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side ** dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side 0.016 ?0.050 (0.406 ?1.270) 0.015 0.004 (0.38 0.10) 45 0 ?8 typ 0.007 ?0.0098 (0.178 ?0.249) 0.053 ?0.068 (1.351 ?1.727) 0.008 ?0.012 (0.203 ?0.305) 0.004 ?0.0098 (0.102 ?0.249) 0.0250 (0.635) bsc 0.337 ?0.344* (8.560 ?8.738) 12 3 4 5 6 7 8 9 10 11 12 0.229 ?0.244 (5.817 ?6.198) 0.150 ?0.157** (3.810 ?3.988) 16171819 2021222324 15 14 13 0.033 (0.838) ref information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen-tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. downloaded from: http:///
16 ltc1755/ltc1756 ? linear technology corporation 1999 sn17556a 17556fs lt/lcg 0800 4k ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear-tech.com part number description comments ltc1514/ltc1515 micropower step-up/step-down inductorless regulated output up to 50ma, v in from 2v to 10v, so-8 package dc/dc converters ltc1516 micropower regulated 5v charge pump 5v/50ma output from 2v to 5v input, s0-8 package ltc1555/ltc1556 sim power supply and level translator step-up/step-down charge pump + generates 3v or 5v ltc1754-5 5v charge pump with shutdown in sot-23 v in from 2.7v to 5.5v, 50ma output with v in 3 3v ltc1986 3v/5v sim power supply in sot-23 v in from 2.6v to 4.4v, 3v/5v output at 10ma related parts typical applicatio u 12 3 4 5 6 7 8 1615 14 13 12 11 10 9 ltc1756 prespwr gnd v in v cc i/orst clk c210 m f n.o. c3 10 m f v cc i/o rst clk c10.68 m f gnd smart card 17556 ta02 smart card present switch m controller 3.3v 5v/3v card ready c c + data rin cin asynchronous smart card interface downloaded from: http:///

▲Up To Search▲

Price & Availability of LTC1755EGNPBF

	To Download LTC1755EGNPBF Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .